Static Timing Analysis (STA) Engineer

STA Design Engineer We need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality. Skills: Overall 3 years industry experience in Backend (Physical Design) STA at SoC level. Hands-on experience with Timing constraints authoring, managing complex clocking, reset, and design hierarchy. Proven experience in minimum 2 Tape-out sign offs. Knowledge of IP and SoC design flows and methodologies Ability to work with local and remote teams (Architecture, RTL, DFT, and Physical Design) Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys) Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability. Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded