Formal verification engineer

Job Title: Formal Verification Engineer

Location: Bangalore

Experience: 4+Years

Job Type: Full-time

Industry: Semiconductor / ASIC Design / EDA

Education: B. E./B. Tech or M. E./M. Tech in ECE/EEE/Computer Engineering

Job Description:

We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and So C designs.

Key Responsibilities:

Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, sequential equivalence checking, and formal coverage. Analyze formal results, identify unreachable or vacuous properties, and refine models. Collaborate closely with RTL designers, DV engineers, and architects. Integrate formal into overall verification methodology and sign-off. Document and present formal verification methodologies, assumptions, and results.

Required Skills:

4+ years of experience in formal verification using industry tools (e.g., Jasper Gold, VC Formal, Questa Formal, One Spin). Strong knowledge of System Verilog Assertions (SVA) and formal property specification. Solid understanding of digital design concepts and RTL coding in Verilog/System Verilog. Familiar with formal coverage metrics and convergence techniques. Experience in debugging complex design bugs using formal tools. Ability to abstract and model designs or protocols at different levels.

Desirable Skills:

Familiarity with safety-critical designs (ISO 26262, DO-254) is a plus. Knowledge of common protocols: AXI, AHB, PCIe, Ethernet, etc. Exposure to sequential equivalence checking and abstraction modeling. Understanding of simulation-based verification and integration with formal. Proficiency in scripting (Python, Perl, or TCL) for automation.

Interested can Share CV to sharmila.b@