Senior rtl design engineer

Job Description:

Role: Senior RTL Design Engineer

Experience: 6 - 12 Years of Experience

Location: Bangalore/ Hyderabad

Work Mode: Work from office

Required Skills

Experience in Logic design / RTL coding is a must. Experience is So C design and integration for complex So Cs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, So C clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills