Memory Layout Engineer

Hiring: Memory Layout Engineers Experience: 2–6 Years Locations: Bangalore | Noida | Hyderabad Notice Period: Immediate Joiners / Short Notice Preferred Key Responsibilities: Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks. Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts. Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization . Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification . Good understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization . Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre . Knowledge of Memory Compiler / Tiling / Automation is an added advantage. Exposure to SKILL / Perl / TCL / Shell scripting is a plus. Education: BE/B.Tech/M.Tech in ECE, EE, VLSI, Microelectronics or related field. Ideal Candidate: Memory/Custom Layout Engineer with strong hands-on implementation and physical verification experience. Current industry postings similarly emphasize Virtuoso, DRC/LVS, memory arrays and physical verification. Interested candidates can share their updated CV with: Total Experience | Relevant Memory Layout Experience | Current Location | Notice Period | Preferred Location