Principal/Senior Staff Physical Design Engineer (Full-chip/SoC)

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

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Location: San Diego or San Jose, CA
ResponsibilitiesComplete entire physical implementation of the block and chip levelPerform synthesis and physical implementation steps – synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffsAnalyze the quality of the floorplan and Customized Clock tree structure and Place & RouteImplement ECOs for timing closureSignal EM/Noise and Power IR/EM analysis and fixDRC/LVS/ERC/ANTENNA analysis and clean upTiming verification and sign-offPhysical verification and sign-off
Minimum QualificationsMaster’s degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor’s degree in electrical/computer science engineering plus 15+ years of industry experienceStrong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoCNetlist (or RTL)-GDS physical implementation experienceIn depth knowledge of major EDA tools/design flows xzbcwsv Strong Cadence experience/backgroundExperience with TSMC N22 or below technologyExperience in chip integration and signoffExperience in Perl/TCL language programming
Preferred QualificationsStrong experience in Low-power implementation methodologyStrong experience in Advanced timing signoff methodologyKnowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flowsAble to independently complete Netlist-GDS P&R, signoff taskProven record in multi-million gate design production tapeouts