Principal Engineer - ASIC Design

TIH | IIT Bombay · India

Job Description:

• Derive sensor-based system level specifications and the circuit architecture
• ASIC design and tapeout
• Coordinate with the fab (interact with chip Manufacturing lab team on the PDK (process design kit), ESD (for I/O's) and other technological aspects.
• Mentor embedded system designer for the ASIC test board design, integration with the ASIC/sensor, circuit testing, set up the prototype characterization work bench
• Field visit along with the engineers for the field testing, interact with the customers on the sensor-system requirements
• Preparation of technical reports (design, testing & validation, field experiments), experimental datasets, mentor engineers for project documentation
• Conduct prior-art and patent search, identify novelty for advancing sensor design, contribute to publications and technology-transfer activities

Minimum Qualifications and Experience:

• Ph.D. in Electrical Engineering or Electronics Engineering, with a thesis related to Integrated Circuit Design, preferably in Analog/Mixed-Signal IC Design.
• Prior experience in IC design and tape-out in an academic or industrial environment.
• Strong publication record or demonstrated experience in IC design and chip testing, particularly in analog/mixed-signal circuits, is preferred.

Required Skills:

• Ability to interpret domain-specific sensing requirements and translate them into circuit specifications.
• Strong knowledge of low-power and low-noise circuit design techniques.
• Experience in sensor signal-conditioning IC design, calibration, and characterization.
• Full ASIC design flow: System level design → Circuit level design → simulation → layout → pre-manufacturing and sign off → tapeout coordination with the fab (Analog & mixed-signal IC design), ASIC testing and running the experiments
• Hands-on experience with IC design flows using Cadence, Synopsys, or Siemens EDA toolsets

Location of work:

• TIH-IoT, IIT Bombay Campus, Powai, Mumbai – 400076.