Senior ASIC Physical Design Engineer

Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure). Experience in Python, Tcl, or Perl scripting. Preferred Qualifications Experience working with external partners on Physical Design (PD) closure. Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates. Experience with Synopsys/Cadence PnR tools. Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.). Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-off