Analog Layout Engineer

Axiro Semiconductor · India

Axiro Semiconductor is a fabless semiconductor design company headquartered in Bengaluru, driving innovation in RF, wireless infrastructure, satellite communication (Satcom), and high-speed connectivity solutions. Backed by CG Power & Industrial Solutions Ltd. part of the 120-year-old Murugappa Group. Axiro represents India’s leap into the global semiconductor arena. With millions of chips already powering global networks, a world-class team across India, the US, and Europe, and cutting-edge expertise spanning RF, mmWave, GaN, and next-generation communication technologies, Axiro is engineering the future of how the world connects, computes, and communicates.

Job Description

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs, etc.)

• Lead, mentor, and review the work of a team of junior layout engineers, providing technical guidance and quality oversight

• Plan, prioritize, and manage layout execution across multiple concurrent projects, coordinating schedules and resources to meet tapeout deadlines

• Drive layout strategy and technology qualification across multiple process nodes and technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD)

• Collaborate with design engineers to optimize layout for performance, area, and reliability

• Perform layout verification, including DRC, LVS, and parasitic extraction

• Apply layout techniques to mitigate issues such as crosstalk, IR drop, and latch-up

• Provide support for post-layout simulations and tapeout activities

• Maintain design documentation and participate in peer layout reviews

• Interface with packaging and assembly teams to ensure compliance with manufacturing rules

• Work with the design and the foundry team for wafer step plan and wafer matrix

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Qualifications & Requirements

• Experience: 12-15 years of hands-on experience in RFIC/MMIC/analog/mixed-signal/custom layout design across multiple process technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD), including experience managing multiple concurrent projects and mentoring junior layout engineers.

• Leadership & Project Management:

o Proven track record managing multiple layout projects simultaneously, from planning through tapeout

o Experience leading, mentoring, and reviewing the work of junior layout engineers, including technical training and career development

o Strong cross-functional coordination with design, verification, program management, and foundry teams to align priorities and schedules

• Technical Expertise:

o Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers

o Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus

• Process Knowledge: Proven experience working across multiple process technologies, including SiGe, BiCMOS, SOI, and BCD, with the ability to ramp new nodes quickly and guide the team through technology-specific layout considerations

• Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations

• Tools Proficiency:

o Experienced with Cadence and Calibre tools in a Linux environment

o Scripting skills in SKILL and Perl are desirable

• Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts

• Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus

• Soft Skills:

o Strong problem-solving and debugging skills

o Effective communication and teamwork

o Flexible, adaptable, and collaborative working style

o Proven leadership skills, including mentoring, delegating, and providing performance feedback to junior engineers

o Strong organizational skills to manage multiple projects and competing priorities