Principal, Sr Staff & Staff Physical Design Engineers (US Citizens)

Huntech USA LLC · San diego, United States

Our marquee customer is looking to address key areas which include:

• Place and Route (with floorplanning experience)
• Timing Closure (with Timing ECO's and a familiarity with DMSA / Primetime/ Tweaker)
• Physical Verification (Calibre/ ICvalidator/ Quantus)
• Overall Physical Design expertise, with strong familiarity across the Synopsys and Cadence tool suites
• Architect and implement robust, low-skew, power-efficient clock distribution networks tailored for a complex cybersecurity design to meet performance, power, and area goals.
• Support physical verification including DRC, LVS, and antenna checks.
• Debug and resolve physical verification violations, working closely with layout, design, and CAD teams.
• Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.
• Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.
• Perform full-chip and block-level STA.
• Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners.
• Debug and resolve setup, hold, and transition violations across various PVT corners.
• Drive timing closure through iterative optimization and ECO implementation.
• Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability.
• Analyze clock tree timing, including skew, latency, and jitter impacts.
• Support signoff timing verification, including cross-domain timing and false/multicycle path handling.

Qualifications

• BS/MSEE with extensive experience in physical design, with a focus on clock tree design and implementation.
• Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.
• Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.

Interested, please email your resume and we can set up a video call.