Memory Circuit Design Lead

leadIC Design Pvt Ltd · India

Location: Noida/Bengaluru/Hyderabad

Experience: 8+ Years

Employment Type: Full-time

Job Overview

We are looking for an experienced Memory Circuit Design Engineer to join our semiconductor design team and work on the design and development of advanced memory circuits and memory macros.

The ideal candidate will have strong hands-on experience in transistor-level memory circuit design , memory architecture, circuit optimization, SPICE simulation, and PVT/corner analysis. The role will involve working closely with architecture, layout, characterization, verification and physical design teams to deliver robust, high-performance and low-power memory solutions.

Key Responsibilities

• Design and develop memory circuits and memory macros at transistor level.
• Work on memory architectures such as SRAM, Register File, ROM and/or DRAM , depending on project requirements.
• Develop and optimize critical memory circuits including:

Memory bitcells

Sense amplifiers

Write drivers

Precharge/equalization circuits

Row/column decoders

Wordline drivers

Column muxing

Address buffers

Read/write control circuits

Assist circuits

Timing/control circuits

• Perform schematic design and transistor-level simulations using SPICE-based simulators.
• Analyze memory performance across PVT corners, voltage ranges and temperature conditions .
• Optimize memory designs for:

Read/write performance

Access time

Leakage power

Dynamic power

Area

Stability

Yield and robustness

• Perform Monte Carlo and statistical analysis to evaluate process variation and mismatch.
• Analyze memory failure mechanisms including read stability, write ability, leakage, disturb conditions and sense-margin issues .
• Develop and optimize memory circuits for low-voltage and low-power operation .
• Work with layout engineers to ensure robust implementation and minimize layout-dependent effects.
• Review and analyze post-layout simulations , including extracted parasitics.
• Support characterization of memory macros across different PVT conditions.
• Debug circuit-level issues and identify root causes of performance, functionality or yield degradation.
• Collaborate with architecture, layout, verification, characterization and technology teams throughout the design cycle.
• Contribute to design reviews, technical documentation and design methodology improvements.
• Support silicon bring-up, silicon correlation and post-silicon debug , wherever applicable.

Required Skills & Experience

• 8+ years of hands-on experience in Memory Circuit Design / Memory IC Design.
• Strong experience in transistor-level circuit design .
• Strong understanding of CMOS circuit design and semiconductor device fundamentals .
• Hands-on experience with one or more memory technologies:
• SRAM
• DRAM
• Register File
• ROM
• Strong understanding of memory architecture and critical memory circuits.
• Experience designing and optimizing bitcells and peripheral circuits .
• Strong hands-on experience with SPICE simulations and circuit-level debugging.
• Experience with Cadence Virtuoso and Spectre or equivalent tools.
• Strong experience with:
• PVT analysis
• Monte Carlo analysis
• Corner analysis
• Post-layout simulation
• Parasitic analysis
• Understanding of memory timing and performance parameters .
• Experience with circuit optimization for power, performance, area and robustness .
• Strong understanding of process variation, mismatch and reliability considerations.
• Ability to work independently on circuit design problems and drive them to closure.

Preferred / Good-to-Have Skills

• Experience with advanced CMOS/FinFET technology nodes .
• Experience with high-density SRAM or embedded memory macros .
• Experience with high-speed memory design .
• Experience with low-voltage SRAM design .
• Knowledge of:
• SRAM stability
• SNM
• Write Margin
• Read Margin
• Assist techniques
• Leakage reduction
• Variation-aware design
• Sense amplifier offset
• Bitline architecture
• Experience with DRAM peripheral circuit design , if applicable.
• Exposure to memory compiler / memory macro development .
• Experience with memory characterization and Liberty/model generation.
• Familiarity with Calibre DRC/LVS/PEX and post-layout verification.
• Experience working with advanced-node design challenges .
• Scripting knowledge in Python, Perl, Tcl or SKILL is a plus.
• Experience with silicon correlation and post-silicon debug is highly desirable.

Tools

Primary:

• Cadence Virtuoso
• Spectre / Spectre X / FastSPICE

Physical Verification / Extraction:

• Calibre
• PEX / RC extraction tools

Simulation / Analysis:

• SPICE
• Monte Carlo
• PVT / Corner Analysis

Scripting:

• Python
• Tcl
• Perl
• SKILL

Education

• B.E./B.Tech/M.E./M.Tech in Electronics & Communication, Electrical Engineering, VLSI or related disciplines .