Senior/ staff memory layout engineer
Prodapt ASIC Services · Bengaluru, India
FULL TIMEpermanent
Job Description
About Prodapt
Prodapt is a global leader in the \"Connectedness\" industry and a certified Great Place To Work®. We are part of the 130-year-old Jhaver Group , a conglomerate with over 32,000 employees. Our ASIC & Semiconductor division (formerly Innovative Logic) is a powerhouse in So C design, focusing on advanced nodes (down to 3nm) for 5 G, AI, Io T, and Cloud sectors.
The Role
We are seeking a Memory Layout Engineer to drive the custom layout design of memory blocks. You will collaborate with circuit design teams to ensure performance, area, and reliability targets are met using the latest Fin FET technologies.
Key Responsibilities
Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
Execute and verify DRC/LVS checks and parasitic extraction.
Optimize layouts for area and performance in collaboration with circuit designers.
Apply expertise in deep submicron and Fin FET technologies.
Required Qualifications
Experience: 4+ years in Memory Layout design
Technical Skills: Mastery of Cadence Virtuoso and Calibre/Assura
Node Expertise: Hands-on experience with 2nm to 7nm TSMC processes
Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field
Prodapt is a global leader in the \"Connectedness\" industry and a certified Great Place To Work®. We are part of the 130-year-old Jhaver Group , a conglomerate with over 32,000 employees. Our ASIC & Semiconductor division (formerly Innovative Logic) is a powerhouse in So C design, focusing on advanced nodes (down to 3nm) for 5 G, AI, Io T, and Cloud sectors.
The Role
We are seeking a Memory Layout Engineer to drive the custom layout design of memory blocks. You will collaborate with circuit design teams to ensure performance, area, and reliability targets are met using the latest Fin FET technologies.
Key Responsibilities
Design custom layouts for memory blocks including SRAM, DRAM, ROM, and Register Files.
Execute and verify DRC/LVS checks and parasitic extraction.
Optimize layouts for area and performance in collaboration with circuit designers.
Apply expertise in deep submicron and Fin FET technologies.
Required Qualifications
Experience: 4+ years in Memory Layout design
Technical Skills: Mastery of Cadence Virtuoso and Calibre/Assura
Node Expertise: Hands-on experience with 2nm to 7nm TSMC processes
Education: Bachelor’s or Master’s degree in Electronics Engineering or a related field
Details
| Company | Prodapt ASIC Services |
| Location | Bengaluru, India |
| Type | FULL TIME |
| Niche | tech |
| Experience | permanent |