Formal Verification Engineer

Formal Verification Engineer Experience : 4 to 12 Years Location : Bangalore Job Description Responsible for developing and executing formal verification strategies for IP and SoC blocks. Write and prove assertions using SystemVerilog Assertions (SVA) or PSL. Use tools like JasperGold, VC Formal, or OneSpin to verify complex designs. Collaborate with design and DV teams to integrate formal early in the cycle. Identify corner-case bugs that are hard to detect via simulation. Perform connectivity, X-check, and equivalence checking using formal apps. Debug failures and analyze root causes efficiently. Drive closure with coverage and waiver management. Automate formal flows using scripting (Python, Perl, or Tcl). Document verification plans, results, and sign-off reports. About Company ACL Dig