Analog Layout Engineer
UST · Mumbai, India
FULL TIME
Job Description
Position:
Analog Layout Engineer Experience:
4+ Years
Job Summary: We are seeking a highly motivated
Analog Layout Engineer
to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal circuits, ensuring compliance with technology design rules, matching requirements, and manufacturability constraints.
Key Responsibilities: Develop and implement custom analog, mixed-signal, and RF layouts for advanced semiconductor technologies. Perform layout of critical analog blocks such as: Operational Amplifiers (Op-Amps) Bandgap References LDO Regulators PLLs ADCs/DACs Charge Pumps Data Converters Ensure proper device matching, symmetry, shielding, and parasitic optimization. Conduct floorplanning and placement of analog blocks. Perform layout verification activities: DRC (Design Rule Check) LVS (Layout Versus Schematic) ERC (Electrical Rule Check) Antenna Checks Density Checks Extract parasitics and support post-layout simulation and signoff activities. Collaborate closely with circuit designers, verification engineers, and foundry teams. Debug and resolve layout-related issues to meet performance, area, and schedule targets. Follow foundry design guidelines and process-specific requirements.
Analog Layout Engineer Experience:
4+ Years
Job Summary: We are seeking a highly motivated
Analog Layout Engineer
to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal circuits, ensuring compliance with technology design rules, matching requirements, and manufacturability constraints.
Key Responsibilities: Develop and implement custom analog, mixed-signal, and RF layouts for advanced semiconductor technologies. Perform layout of critical analog blocks such as: Operational Amplifiers (Op-Amps) Bandgap References LDO Regulators PLLs ADCs/DACs Charge Pumps Data Converters Ensure proper device matching, symmetry, shielding, and parasitic optimization. Conduct floorplanning and placement of analog blocks. Perform layout verification activities: DRC (Design Rule Check) LVS (Layout Versus Schematic) ERC (Electrical Rule Check) Antenna Checks Density Checks Extract parasitics and support post-layout simulation and signoff activities. Collaborate closely with circuit designers, verification engineers, and foundry teams. Debug and resolve layout-related issues to meet performance, area, and schedule targets. Follow foundry design guidelines and process-specific requirements.
Details
| Company | UST |
| Location | Mumbai, India |
| Type | FULL TIME |
| Niche | general |