Senior ASIC Physical Design Engineer – RTL2GDS & PPA Expert

Google Inc. · Mountain view, United States

Google is seeking a Senior Physical Design Engineer to deliver full-chip/ASIC implementation with a focus on high performance, area efficiency, and power optimization. You will own RTL2GDS and collaborate with cross-functional teams to push innovations across hardware and software boundaries.

The position requires a strong background in physical design, Verilog/SystemVerilog, and scripting, with experience in top-tier EDA tools. In-person interviews are often part of the process.