M

SoC Design Director

\n

Top40 Semiconductor Organization in the world

\n

Bangalore

\n

Role Overview

\n

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

\n

Key Responsibilities

\n

\n
• Design and implement high-performance digital solutions, including RTL development and synthesis.Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
\n
• Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verificationflows
\n
• Basic Qualifications / Experience Level
\n
• Bachelor's in Electronics/Electrical engineering (Master's prefe
\n
• rred).Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation.Proven expertise in RTL development, synthesis, and timing closure.Experience with front-end design, gate-level simulations, and design verification.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused atttude.
\n

\n

Required Expertise

\n

Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced

\n

nodes (Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O

\n

cycles .Hands-on experience with processor IP (

\n

ARM/ARC)

\n

Experience of working on PCIe is a must

\n

.Hands-on pre-silicon and post-silicon implementing peripherals for I2C/

\n

SPI/UART

\n

Hands-on experience with complex DMA engines and FW interaction

\n

.Strong proficiency in System Verilog/Verilog and scripting (Pytho

\n

n/Perl)

\n

.Experience with block-level and full-chip design at advanced nodes (≤ 16nm)

\n

.Silicon bring-up and post-silicon debug experience

\n

.Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification

\n

.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

\n

Preferred Experience

\n

\n
• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation
\n

\n

is a plus

\n

.Knowledge of system-level design with ARM/ARC/RISC-V processorssub systems

\n

Experience of working on PCIe/UAL isa big plus

\n

.Understanding of PAD design, DFT, and floor planning

\n

.Experience in synthesis, and timing closure is a big plus

\n

.Experience with NIC, switch, or storage product development

\n

.Familiarity with working in design and verification workflows in a CI/CD environment.

\n

Skils

\n

microarchitecture

\n

"rtl design" / "RTL coding" /"RTL Development" /"Logic design"

\n

Synthesis

\n

"timing closure"

\n

ARM

\n

ARC

\n

PCIe

\n

Verilog

\n

SystemVerilog (SV)

\n

UVM

\n

RISC-V

\n

UAL (UALink)

\n

NIC / Sartnic

\n

Switch / Ethernet /"Ultra ethernet"

\n

NVlink

\n

CXL

\n

RISC-V

\n

DMA

\n

Networking

\n

"data center"

\n

Contact: Uday

\n

Mulya Technologies

\n

muday_bhaskar@yahoo.com