RTL (ASIC) Design Engineer

RTL Design Engineer (SDC Constraints) : + : : / We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams. ➖ Design and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystems ➖ Create, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.) ➖ Work closely with synthesis, STA, physical design, and verification teams to achieve timing closure ➖ Perform RTL quality checks, linting, and CDC analysis ➖ Support timing debugging and constraint optimization across multiple design iterations ➖ Participate in architecture