Field-Programmable Gate Arrays Engineer

• Strong Verilog HDL and RTL design expertise.
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• Good knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.• Experience with FPGA tools like Vivado, Quartus, Libero, Questa/ModelSim. xzbcwsv • Strong understanding of STA, timing constraints, timing closure, and clock architecture. • Hands-on experience in FPGA hardware bring-up and debugging