RTL Design Engineers (Train AI Models Part Time!)

hackajob is collaborating with Mercor to connect them with exceptional professionals for this role. About the Role We are sourcing senior digital chip design and verification engineers to support an AI evaluation program focused on frontier silicon / chip-design workflows. We are targeting the next couple of months and will prioritize truly strong contributors who can commit meaningful time. Two parallel profiles - candidates may apply to either track: Track 1: RTL Design Engineer Qualifications - 3-10 years of experience in digital RTL design - Strong proficiency in Verilog / SystemVerilog - Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols - Experience with ASIC design flows: lint, synthesis, timing analysi