RTL - FPGA Design Engineer

ACL Digital · India

RTL & FPGA Design Engineer

Experience : 4-6 years

Location : Hyderabad

Core Skills : RTL Digital Design (Verilog/VHDL), Vivado toolchain (Design creation to Bitstream generation), and timing/IO constraints.

Architecture & Interfaces : Strong grasp of AXI/AHB/CHI/ACE5 buses, peripherals (USB, Ethernet), and Video IPs (ISP/Encoder/Decoder).

Debugging & Tools : Industry-standard front-end waveform debugging, ILA, Unix environment, and scripting (Tcl/Python/Perl).

Bonus : Hands-on experience with pre-silicon platforms and automated verification flows.

Interested candidates, please send your resume t o janagaradha.n@acldigital.c om!