Senior FPGA Design Engineer

Job Description We are developing cutting-edge 5G ready wireless systems solving the rural and urban high bandwidth networking requirements. We are looking for strongly motivated candidates who have hands-on experience in System Verilog programming for wireless baseband design. Participate in the architecture definition, implementation, and test plan development. Develop and implement RTL level blocks, perform synthesis, implement on FPGAs and resolve timing violations. Coordinate with the Software and Hardware team to identify the system issues and resolve the same. Requirements Required skills: 5+ years of work experience and 2+ years of experience in handling team. Strong base in digital design, RTL & FPGA development flows. Proficiency in HDLs like SystemVerilog/Verilog for RTL Design.