RTL Design - Microarchitecture

Role Overview: As an ASIC Design Engineer, you will play a key role in microarchitecture definition, RTL design, and implementation of high-speed interface IPs. You will collaborate with cross-functional teams to deliver high-performance, power-efficient, and scalable silicon solutions. Key Responsibilities: Experience 10yrs , Bangalore location Architect and design high-performance ASIC SoCs, targeting high-speed protocols such as PCIe Gen4/5, 100G/400G Ethernet, USB3/4, SerDes-based interfaces. Develop RTL using Verilog/System Verilog with a focus on performance, power, and area (PPA) optimization Define and document micro-architecture and interface specifications for protocol IPs Collaborate with verification teams to develop test plans, debug failures, and achieve coverage closure Work closely with physical design teams on synthesis, timing closure, and floor planning support Analyze and debug silicon bring-up issues related to high-speed interfaces Integrate third-party IPs (SerDes, PHYs) and ensure proper functionality and interoperability Participate in design reviews and ensure adherence to design methodologies and best practices Drive design quality through lint, CDC, and verification readiness checks Required Skills: Strong experience in RTL design using Verilog/System Verilog. Deep understanding of high-speed protocols , such as: PCIe (Gen4/Gen5), Ethernet (100G/400G), USB (USB3/USB4), SerDes-based architectures. Solid background in microarchitecture design and trade-off analysis Experience in SoC integration and subsystem design Good knowledge of synthesis, STA, and physical design considerations Good to Have: Experience in silicon bring-up and post-silicon debug Exposure to advanced technology nodes and high-frequency designs Scripting skills (Python/Perl/Shell) for automation What We’re Looking For: Strong debugging and analytical skills Ability to work across cross-functional teams Ownership mindset and attention to detail Passion for building high-performance silicon