Senior Memory Layout Engineer

LeadSoc Technologies Pvt Ltd · India

Senior Memory Layout Engineer

Location: Hyderabad, India

Experience: 5–10 Years

Role Overview:

We are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts.

Key Responsibilities:

• Develop custom layouts for memory circuits including SRAM, ROM, Register File, and memory periphery.
• Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database .
• Work on layout of bitcells, sense amplifiers, pre-charge circuits, decoders, write/read paths, and peripheral circuits .
• Perform matching, symmetry, shielding, common-centroid, and parasitic-aware layout as applicable.
• Debug and resolve DRC, LVS, ERC, antenna, density, and connectivity issues.
• Collaborate with circuit designers on layout optimization, PPA, matching, and parasitic reduction .
• Support PEX and post-layout simulation activities.
• Ensure adherence to foundry PDK, design rules, and layout methodologies .
• Participate in design reviews, tapeout activities, and continuous layout methodology improvements.

Required Skills:

• 5–10 years of relevant experience in Memory / Custom IC Layout.
• Strong hands-on experience with SRAM and/or memory macro layout .
• Good understanding of CMOS layout concepts, device matching, parasitics, and design rules .
• Experience with industry-standard tools such as Cadence Virtuoso, Calibre, or equivalent .
• Strong expertise in DRC/LVS debugging and physical verification .
• Understanding of FinFET/advanced-node layout concepts is preferred.
• Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage.
• Strong analytical, debugging, and cross-functional collaboration skills.

Preferred

• Experience with high-density memory macros and advanced-node technologies .
• Exposure to full-custom layout, PEX, EM/IR, and reliability checks .
• Experience working in a tapeout-driven semiconductor environment .