Senior rtl design engineer

Senior RTL Design Engineer

Location: Hyderabad

Experience: 3–6 Years

Role Overview

We are looking for a Senior RTL Design Engineer with strong hands-on expertise in Ethernet-based So C/IP design, RTL development, and design quality checks.

Key Responsibilities

Develop and integrate synthesizable RTL for complex So C/IP designs. Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs. Translate microarchitecture specifications into efficient RTL. Perform Lint, CDC/RDC and RTL quality checks using Spy Glass. Debug and resolve RTL, CDC, lint and functional issues. Collaborate with Architecture, DV, STA and Physical Design teams. Drive RTL optimization for PPA, timing, area and power.

Core Technical Skills

Strong Verilog/System Verilog RTL design experience. Solid microarchitecture understanding and ability to work from specifications. Strong Ethernet knowledge — MAC/PCS/PHY, 10 G/25 G/100 G/400 G exposure preferred. Hands-on experience with Spy Glass Lint & CDC. Strong understanding of CDC, reset architecture, clocking and RTL coding practices. Experience with synthesis, timing and PPA optimization. Strong debugging and problem-solving skills.

Ideal Candidate: A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + Spy Glass expertise and experience delivering production-quality So C/IP designs.