RTL Design Engineer Role

RTL Design Engineer | 5-12 Years We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation. Key Requirements: Strong experience in RTL design using Verilog/SystemVerilog or VHDL Hands-on experience in ASIC/SoC development Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs Experience in functional verification and RTL debugging Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC. Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle Good to Have: Exposure to UVM-based verification environments Experience with Python, Perl, or Shell scripting Familiarity with STA and synthesis flows Qualification: Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field Why Join Us? Opportunity to work on cutting-edge ASIC/SoC technologies Collaborative and fast-paced engineering environment Strong learning and career growth opportunities Competitive compensation and benefits package