Senior Physical Design Lead - SoC Floorplanning & Integration

Mulya Technologies · India

Location: Bengaluru, India

Experience: 5-16 years

Industry: Semiconductors | AI | Networking | ASIC Design

Senior Physical Design Lead - SoC Floorplanning & Integration

Location: Bengaluru, India

Experience: 12-20 years

Industry: Semiconductors | AI | Networking | ASIC Design

Role Overview

We are seeking a hands-on Senior Physical Design Lead to own full-chip SoC physical implementation for our next-generation AI-networking silicon. You will define the top-level floorplan and partitioning strategy, personally drive chip-level integration and convergence, and lead a small team of block/partition owners from netlist to tape-out. This is a working-lead role - you set the SoC floorplan vision and stay hands-on in the tool on the hardest full-chip problems.

Key Responsibilities

• SoC Floorplanning Ownership: Define and own the full-chip floorplan - top-level partitioning, block placement, aspect ratios, macro and IP placement, IO/bump planning, and die-size budgeting.
• Partitioning Strategy: Drive hierarchical partitioning, feedthrough planning, and pin/budget allocation across partitions to enable parallel block development.
• Top-Level Integration: Own chip-level assembly, top-level routing, clock and reset distribution, and full-chip timing/physical convergence.
• Power Delivery Co-Design: Work with the PDN and EM/IR teams to co-design the power grid and floorplan so power-integrity and reliability targets are met from the start.
• Working Leadership: Lead and mentor block/partition PD engineers while staying hands-on; set QoR targets and review cadence across the SoC.
• Cross-Functional Alignment: Partner with architecture, RTL, STA, DFT, packaging, and foundry teams to align floorplan and integration decisions.
• Convergence & Tape-out: Drive full-chip timing, congestion, IR, and physical-verification closure and own the SoC through sign-off and tape-out.
• Schedule & Risk: Plan SoC PD milestones, surface floorplan and integration risks early, and drive mitigation.

Key Skills

• SoC Floorplanning Mastery: Proven, hands-on expertise defining full-chip floorplans and hierarchical partitioning for large, complex SoCs.
• Full-Chip Integration: Deep experience with top-level assembly, chip-level routing, clock distribution, and full-chip timing closure.
• Place & Route Tools: Expert with Synopsys Fusion Compiler/ICC2 and/or Cadence Innovus, including hierarchical and top-down flows.
• Sign-off Breadth: Strong working knowledge across PrimeTime (STA), Calibre/ICV (PV), and RedHawk/Voltus (power integrity).
• Power & Reliability: Understanding of PDN design, IR-drop, and EM and how floorplan choices drive power integrity.
• Leadership: Ability to lead and mentor PD engineers while remaining hands-on on the toughest blocks.
• Scripting: Expert in TCL with strong Python and/or Perl for flow development and automation.
• Process Technology: Extensive hands-on experience on advanced FinFET nodes (7nm/5nm and below); 3nm exposure is a plus.

Preferred Qualifications

• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience leading SoC-level floorplanning and integration for high-speed networking or large AI/accelerator chips.
• Hands-on experience with multi-die / chiplet floorplanning, 2.5D/3D integration, and package-aware planning.
• Track record of taking at least one large SoC from concept floorplan through successful tape-out and silicon bring-up.

Startup mindset - able to build and run flows from scratch in a fast-paced, high-execution environment.