Memory layout engineer

Memory Layout Engineer

Experience: 4–8 years

Location – Bangalore

Qualifications:

Bachelor's or Master's degree in Electrical Engineering,

Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes

Key Skills & Responsibilities:

Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc. Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits Expertise in top-level memory integration, DRC, LVS, density verification, and physical closure Understanding of IR/EM challenges in memory layouts Proficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verification Exposure to ultra-deep sub-micron design challenges and DFM guidelines Knowledge of memory architecture, bitcell layout concepts, and Fin FET design rules Ability to optimize layout for area, power, speed, yield, and manufacturability Collaboration with circuit design, verification, PDK, and methodology team