Analog Layout Engineer

Job Description: 4 – 6+ years of hands-on block-level Analog Layout (Custom & RF) experience. Experience should be on FinFET nodes, preferably 3–7nm. Experience in Samsung 8nm, TSMC 7nm, and TSMC 16nm; Samsung 8nm is an advantage. Strong knowledge of Analog/RF layout techniques and current industry methodologies. Experience in circuit design analysis, layouts, LVS/DRC/ERC checks, and ESD verification for high-complexity RF designs. Candidates should have successfully completed a couple of full project cycles from floor plan to tape-out. Good knowledge of ESD, LOD, WPE, Latch-up, IR drop, and EM issues and fixes.