Senior lead engineer
Eximietas Design · Bengaluru, India
FULL TIMEpermanent
Job Description
Design for Test (DFT) Opportunities
We are looking for passionate and driven Design for Test (DFT) professionals to join our growing team and contribute to cutting-edge silicon development.
Whether you are:
A hands-on technical expert who thrives on solving complex implementation challenges, or
A senior leader/architect with deep industry experience shaping DFT strategies across advanced nodes,
we have exciting opportunities that will challenge your skills and accelerate your career.
## Core Responsibilities
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery. Key focus areas include:
Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC.
Block level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization.
Verification: Handling Pattern simulations (both Timing and Non-timing).
SOC Integration: Pattern Retargeting to SOC/Subsystem levels and performing full-chip simulations.
Memory & IP Test: Integration and simulation of MBIST, IJTAG, and Boundary Scan (JTAG).
Debug & Analysis: Independent debugging of DFT simulations and netlist handling.
### Technical Requirements
Must-Have Skills:
Netlist Management: Handling of netlists and ATPG simulations.
Pattern Retargeting: Proven experience in retargeting block-level patterns to top-level and subsequent simulation debug.
Standards: Deep understanding of ICL/PDL.
Tools: Handling of at least one major tool suite:
Siemens (Tessent)
Synopsys (Test MAX / Tetra MAX)
Cadence (Modus)
Preferred & Advanced Skills:
Experience with SSN (Streaming Scan Network).
Knowledge of Analog DFT methodologies.
Proficiency in Spy Glass for DFT linting and early analysis. Handling of RTL level DFT.
### What We Are Looking For
Mid-Level (5-10 Years): Strong execution focus, ability to own blocks independently, and proficiency in simulation debug.
Senior/Principal (10-25 Years): Ability to define DFT strategy, architect SOC-level test solutions, mentor junior engineers, and interface with design/foundry teams.
Interested candidates can share their profiles at:
We are looking for passionate and driven Design for Test (DFT) professionals to join our growing team and contribute to cutting-edge silicon development.
Whether you are:
A hands-on technical expert who thrives on solving complex implementation challenges, or
A senior leader/architect with deep industry experience shaping DFT strategies across advanced nodes,
we have exciting opportunities that will challenge your skills and accelerate your career.
## Core Responsibilities
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery. Key focus areas include:
Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC.
Block level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization.
Verification: Handling Pattern simulations (both Timing and Non-timing).
SOC Integration: Pattern Retargeting to SOC/Subsystem levels and performing full-chip simulations.
Memory & IP Test: Integration and simulation of MBIST, IJTAG, and Boundary Scan (JTAG).
Debug & Analysis: Independent debugging of DFT simulations and netlist handling.
### Technical Requirements
Must-Have Skills:
Netlist Management: Handling of netlists and ATPG simulations.
Pattern Retargeting: Proven experience in retargeting block-level patterns to top-level and subsequent simulation debug.
Standards: Deep understanding of ICL/PDL.
Tools: Handling of at least one major tool suite:
Siemens (Tessent)
Synopsys (Test MAX / Tetra MAX)
Cadence (Modus)
Preferred & Advanced Skills:
Experience with SSN (Streaming Scan Network).
Knowledge of Analog DFT methodologies.
Proficiency in Spy Glass for DFT linting and early analysis. Handling of RTL level DFT.
### What We Are Looking For
Mid-Level (5-10 Years): Strong execution focus, ability to own blocks independently, and proficiency in simulation debug.
Senior/Principal (10-25 Years): Ability to define DFT strategy, architect SOC-level test solutions, mentor junior engineers, and interface with design/foundry teams.
Interested candidates can share their profiles at:
Details
| Company | Eximietas Design |
| Location | Bengaluru, India |
| Type | FULL TIME |
| Niche | tech |
| Experience | permanent |